The present invention relates to a technique, which is particularly applicable to a read method for multiple-value information in a semiconductor memory and, moreover, is effective for a nonvolatile semiconductor memory. More particularly the invention is applicable to a technique which may be effectively used for a nonvolatile memory (hereafter referred to as a flash memory) to electrically simultaneously erase a plurality of stored pieces of information.
A flash memory uses a nonvolatile memory cell having a control gate and a floating gate as a memory cell. It is possible to constitute the memory cell of one transistor. In the case of a write operation of the flash memory, as shown in FIG. 16, a state in which the threshold voltage is low (logic "0") is set up by setting the drain region of a nonvolatile memory cell at approx. 5 V (volt) and a word line connected with a control gate CG at approx. -11 V and, thereby, extracting electric charges from a floating gate FG by means of a tunnel current. In the case of an erase operation, as shown in FIG. 17, a state in which the threshold voltage is high (logic "1") is set up by setting a well region, drain region and source region at approximately 0V and the control gate CG to a high voltage, such as 16V, thereby generating a tunnel current, and injecting negative electric charges into the floating gate CG. During the read operation, it is judged that the data stored in a memory cell through which current flows is "0" and a memory cell through which no current flows is "1" by setting the control gate at an intermediate voltage between a high threshold and a low threshold and detecting whether current flows or not. Thereby, one-bit of data is stored in one memory cell.
A technique has been proposed, which is related to the so-called multiple-value memory, for storing data of two bits or more in one memory cell in order to increase the memory capacity. An invention related to the multiple-value memory is disclosed in Japanese Patent Application No. 14031/1995, etc.
Such a multiple-value memory stores information by controlling the amount of electric charges to be injected into a floating gate, thereby stepwise changing thresholds to 1 V, 2V, 3V, . . . , and making information of a plurality of bits correspond to each threshold value. FIG. 18 shows a threshold value distribution state when storing information by dividing one memory cell into four threshold value states (this will be referred to as four-value state in this specification). It is difficult to accurately control the threshold value of a memory cell to a predetermined value for a write operation, and therefore, as shown in FIG. 18, a normal distribution is established around each target threshold voltage. To read data, voltages corresponding to the valleys of the threshold value distributions are read, set as VRW1, VRW2, and VRW3, and applied to a control gate through a word line. In this case, the drain is set at a potential, such as 1V, and the source is set at a potential, such as 0V. The bit-line precharging method can be used for the setting of the drain voltage.
Table 1 shows the results of reading data from memory cells belonging to the threshold value distributions A, B, C, and D by using the above read voltages VRW1, VRW2, and VRW3 (VRW1&lt;VRW2&lt;VRW3). Because the memory cell belonging to the threshold value distribution A has the highest threshold value, no current flows even if any one of VRW1, VRW2, and VRW3 is applied. Therefore, the read result is "1". In the case of the memory cell belonging to the threshold value distribution B, the read result is "1" because no current flows when VRW1 or VRW2 is applied. However, when VRW3 is applied, the read result is "0" because current flows. In the case of the memory cell belonging to the threshold value distribution C, the read result is "1" because no current flows when VRW1 is applied. However, when VRW2 or VRW3 is applied, the read result is "0" because current flows. In the case of the memory cell belonging to the threshold value distribution D, the read result is always "0" in any case because current flows if any one of VRW1, VRW2, and VRW3 is applied. Though a case of a four-value memory has been described above, the same holds theoretically for eight- and sixteen-value memories.
TABLE 1 Memory A Memory B Memory C Memory D VRW3 1 0 0 0 VRW2 1 1 0 0 VRW1 1 1 1 0